The iCD Design Integrity software incorporates the Stackup, PDN and CPW Planner plus a myriad of new functionality specifically developed for high-speed PCB design. The following is a description of the latest features.
The iCD CPW Planner
iCD is please to announce the release the new iCD CPW Planner to be incorporated as part of the 2017 release of its suite of high-speed PCB design tools. Coplanar Waveguides (CPWs) have been used for many years in RF and microwave design as they reduce radiation loss, at extremely high frequencies, compared to traditional microstrip. And now, as edge rates continue to rise, they are coming back into vogue. Today’s high-speed, fast rise time serial interfaces are prone to excess loss, in the transmission lines, which is a major cause of signal integrity issues. Minimizing this loss reduces jitter and improves the bit error rate (BER) and inter-symbol interference (ISI).
The CPW offers several advantages over a conventional microstrip transmission line:
Furthermore, the impedance is determined by the ratio of trace width to clearance, so size reduction is possible without limit, the only penalty being higher losses.
The new iCD CPW Planner has five popular generic CPW structures that model single and dual (differential) CPWs, with and without ground reference planes, plus a dual Coplanar Strip (CPS) which has no ground reference plane or copper pours. Materials maybe inserted, from the extensive iCD Dielectric Materials Library featuring over 30,850 rigid and flexible materials up to 100GHz, to dramatically increase accuracy at extremely high microwave frequencies.
Click here for a quick demonstration video of the iCD Coplanar Waveguide Planner.
The iCD Termination Planner
For perfect transfer of energy and to benefit from the highest possible bandwidth, the impedance of the driver must match the impedance of the transmission line and be constant along its entire length. Unfortunately, using mainstream PCB layout software, one really has no idea what the driver impedance is, let alone the capability to match the driver to the unknown impedance of the transmission line. The iCD Termination Planner addresses this issue.
Firstly, the attributes required to determine the source impedance of the driver, are extracted from an IBIS model IV curves. Then the required series termination resistance is calculated, based on a distributed system, to match the transmission line for the selected layer in the iCD Stackup Planner. If the IBIS model is not available (or produces an error) the user may use Generic models to calculate an approximate series termination. Generic models include: typical DDRx, Display Port, ECL, HDMI, LVCMOS and LVTTL gates, Mini-LVDS, NAND Flash, PCI, SDRAM, HSTL and SSTL models.
The number of loads, on the transmission line, also has an affect on the required value of series termination; as the IC input inductance and capacitance tend to roll-off the signal rise time. This can be adjusted from 1 – 6 loads and automatically compensated for in the calculation.
A quick demonstration of the new iCD Termination Planner can be viewed here.
Matched Delay Optimization
Matched length does not equal matched delay!
Signals propagate at the speed-of-light in free space. However, this speed varies dramatically depending on the surrounding dielectric materials. Each layer, of a multilayer PCB, can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The new 'Relative Signal Propagation' feature, of the iCD Stackup Planner, allows you to not only match the length of busses, but takes this one step further by automatically simulating the appropriate length required to match the delay exactly. The integrated field solver simulates the inductance, capacitance and flight time, of each signal layer, to quickly give you the results you need to effectively route memory busses.
IPC-2581B Bi-directional Interface
The iCD Stackup Planner - IPC-2581 bi-directional interface allows the user to import stackup files from EDA tools that support the format, edit the stackup and then export, together with the original board data back into IPC-2581 A & B format. Alternatively, you can start with the Stackup Planner and export this directly to IPC-2581 format.
This new feature gives the iCD Stackup Planner the ability to import/export Cadence Allegro 16.6 and OrCAD 16.6 stackups and to import Altium Designer and Zuken CR-8000 & CR-5000 stackups. The enduring Gerber format can transfer image data to manufacturing, but it cannot transfer stackup data, materials information, design intent, or net lists. Supporting IPC-2581B opens a new level of communications with the PCB manufacturing and assembly sector that is long overdue.
The iCD Stackup Planner - Allegro Interface exports the stackup from the Stackup Planner into Cadence Allegro PCB. Please note: The new IPC-2581B bi-directional interface may be more appropriate for Allegro & OrCAD 16.6 users as it allows both export and then import of the stackup back into Allegro.
Altium Designer Interface
The Altium Designer (AD16) - iCD Stackup Planner bi-directional interface exports the substrate configuration from iCD Stackup Planner, automatically creating the corresponding Layers in Altium Designer’s Layer Stack Manager. Also, Design Rules for Via Spans, Trace Width, Clearance and Differential Pairs are automatically created in Altium Designer, enabling the user to route each layer and differential pair to the calculated single ended or differential impedance. The interface utility can also export multiple stacks of rigid/flex Altium Designer Layers from the Layer Stack Manager and Trace Width/Clearances into iCD Stackup Planner for the calculation of impedance and trace current. The stackup can then be modified in Stackup Planner—to obtain the desired impedances—and then imported back into Altium Designer.
Watch the videos Altium Designer AD14-17 to iCD Stackup Planner Bi-directional Interface (7:15 minutes)
Altium Designer Rules creation (4:35 minutes)
The Stackup Planner/PADS Layout bi-directional interface exports Mentor Graphics' PADS Electrical Layers into iCD Stackup Planner for the calculation of impedance and trace current. The stackup can then be modified in Stackup Planner to obtain the desired impedances and imported back into PADS Layout. This interfaces uses the PADS v5.0 ASCII format so it is compatible with all the latest versions.
PADS video also available at PADS PCB to iCD Stackup Planner Bi-directional Interface (6 minutes)
The bi-directional Mentor Graphics' HyperLynx interface imports and exports .ffs and .stk files from/to LineSim and BoardSim to the iCD Stackup Planner. The stackup can modified to add materials from the extensive dielectric materials library and to fine tune impedance.
HyperLynx, LineSim and BoardSim video at HyperLynx to iCD Stackup Planner Bi-directional Interface (10:45 minutes)
Please make Secure Payment
© Copyright 1996-2017 In-Circuit Design Pty Ltd.
This web site was produced by In-Circuit Design Pty Ltd. All trademarks are registered trademarks of their respective owners.