iCD Stackup Planner
"For Engineers and PCB Designers involved in high-speed design, the iCD Stackup Planner offers unprecedented simulation speed, ease of use and accuracy at an affordable price".
The iCD Stackup Planner features a precision 2D Boundary Element Method (BEM) Field Solver providing customers with the accuracy and simulation speed they need for high-speed PCB Design. Seamless integration with the Altium Layer Stack Manager, allows the transfer of substrate materials for the correct trace impedance and automatic creation of Design Rules for differential pairs and trace routing. Bi-directional Interfaces are also available to other EDA tools.
Impedance is the key factor that controls the stability of a design - it is the core issue of the signal integrity methodology. A properly planned PCB substrate can effectively reduce electromagnetic emissions, crosstalk and improve signal integrity providing a low inductance power distribution network. It can also improve the manufacturability of the product, reduce costs and increase product performance and reliability.
iCD Stackup Planner On-line Videos:
Differential Pair Definition (4 mins)
The iCD Termination Planner (11:30 mins)
EDA Interface On-line Videos:
Altium Designer 14-18 Interface (7:15 mins)
Altium Designer Automatic Rules Creation (3:35 mins)
HyperLynx Interface 10:45 mins)
IPC-2581B Interface (Allegro, OrCAD, Xpedition, Zuken - 7:15 mins)
Mentor PADS Interface (11:30 mins)
The iCD Stackup Planner is the first controlled impedance tool to enable field solver computation of multiple differential pair definitions per layer. This allows you to incorporate differential 50/100 ohm Digital, 40/80 ohm DDR3/4, 90 ohm USB, 85 ohm PCIe etc sharing the same layers - a stackup planning and documentation tool that can accommodate your differential impedance planning process right out of the box.
The iCD Stackup Planner FX-HDI edition includes a customizable Dielectric Materials Library, taking In-Circuit Design's industry-leading field solver accuracy one more step toward the actual, fabricated circuit board configuration. By collaborating with your preferred PCB fabricator on their standard, off-the-shelf core, prepreg and solder mask materials, what you calculate - in Stackup Planner FX-HDI - is as close to the real thing as you're going to get. The Dielectric Library Editor comes with a comprehensive library of over 31,500 rigid and flexible core, prepreg, and solder mask materials to 100GHz.
With the latest release (March 2018), new materials have been incorporated, into the Dielectric Materials Library, to bring the total count to 31,500. This is arguably the most comprehensive materials library in the PCB industry. For a complete list of the manufacturers and products included in the library please click here.
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In the 2018 release of the iCD Design Integrity software, we have improved the functionality of the library to increase productivity. Dielectric materials can now be selected and inserted, into the iCD Stackup Planner and iCD CPW Planners, in sequence greatly increasing the speed to capture a stackup configuration. Similarly, capacitors can be sequentially inserted into the iCD PDN Planner. Please see the 2 minute video.
Today's high-speed interfaces simply cannot be modeled using a match-to-length methodology - an approach that conventional PCB design tools support. This is because of the tight timing margins. A matched length of 2.3 inches for a DDR3/4 data lane, for instance, can produce up to 70ps delta, between signal layers, leaving the timing way outside the required setup and hold times.
Signals propagate at the speed-of-light in free space. However, this speed varies dramatically depending on the surrounding dielectric materials. Each layer, of a multilayer PCB, can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The 'Matched Delay Optimization' feature, of the iCD Stackup Planner, allows you to not only match the length of busses, but takes this one step further by automatically calculating the appropriate length required to match the delay exactly. The integrated field solver simulates the flight time, of each signal layer, to quickly give you the results you need to effectively route memory.
The relative signal propagation, of each signal layer, is displayed as a bar graph, once the matched length has been set. Selecting 'Match Delay automatically optimizes the length, of each signal layer, to match the maximum delay. The user can then route the data lane, to the exact delay, in their preferred design tool.
Please see the short video Matched Delay Optimization
It is one thing to perfectly match the delay of the transmission lines but unfortunately, using mainstream PCB layout software, one really has no idea what the driver impedance is, let alone the capability to match the driver to the impedance of the transmission line. The iCD Termination Planner addresses this issue.
Firstly, the attributes required to determine the source impedance of the driver, are extracted from an IBIS model IV curves. Then the required series termination resistance is calculated, based on a distributed system, to match the transmission line for the selected layer in the iCD Stackup Planner. If the IBIS model is not available (or produces an error) the user may use Generic Models to calculate an approximate series termination. Generic Models include: typical DDRx, Display Port, ECL, HDMI, LVCMOS and LVTTL gates, Mini-LVDS, NAND Flash, PCI, SDRAM, HSTL and SSTL models.
The number of loads, on the transmission line, also has an effect on the required value of series termination; as the IC input inductance and capacitance tend to roll-off the signal rise time. This can be adjusted from 1-6 loads and automatically compensated for in the calculation.
The Via Span Definition dialog allows the user to insert plated-through-hole (PTH), Blind Microvias - that span from the top or bottom to an internal layer or Buried Microvias that span two or more internal layers and do not come out to either the top or bottom of the board.
The Start and Stop layers are defined, and these may be mirrored so that the same mirrored vias are placed on the bottom side of the board to save time. Finished hole size, Tolerance and the aspect ratio of the board thickness to via diameter is calculated automatically. The aspect ratio should normally not exceed 8:1for PTH or 0.8:1 for microvias.
The vias spans are exported to Excel Fabrication Drawing.
Since all substrates are symmetrical, Stackup Mirroring allows the user to cut data entry time in half. Create the top half of a symmetric stackup, right click on the stackup, and select 'Mirror Stackup'. A central core or prepreg material is automatically inserted in between the two sections (if required).
The impedance plots are simulated by multiple passes of the field solver (in the background) to create heads-up graphs of how to adjust the particular variables to achieve the desired impedance. The impedance plots are launched by selecting a signal or dielectric layer (not plane) in the listview then clicking on the Impedance Plots icon or by selecting them from the RMB menu. You can then click on any layer to get the associated graph for that layer without re-launching the plots.
It is a trade-off between trace width, trace (copper) thickness, dielectric thickness and dielectric constant. Then if you also need to include differential impedance, the trace clearance also comes into play. Plus, one needs to also consider what materials your preferred fab shop has in stock. So determining the correct variable, for your application, is not as simple as clicking an impedance 'goal seeking' button. But rather, one should weigh up all the pros and cons of changing each variable and make an informed decision. That is exactly what the impedance plots allow you to determine.
With differential impedance, there comes a (coupling) point whereby increasing the trace separation or the dielectric thickness has little or no further effect on impedance. At this point, the impedance rolls off and the traces become uncoupled. This is also the point where crosstalk of unrelated signals begins to occur. On the example above, this point is 10 mils. For crosstalk, this point is also the minimum separation before coupling occurs. This gives you a defined clearance rule, to constrain routing, in order to avoid edge coupled crosstalk of long parallel trace segments.